The present invention relates, in general, to flash memory devices and, more particularly, to a flash memory device and an erase method using the same, in which a plurality of blocks are erased at the same time, shortening an erase time.
In general, a NAND flash memory device includes a plurality of cell blocks. One cell block includes a plurality of cell strings in which a plurality of cells are connected in series, a plurality of bit lines, a plurality of word lines, a drain select transistor connected between the cell strings and the bit lines, and a source select transistor connected between the cell strings and a common source line.
Meanwhile, the plurality of memory cells sharing one word line constitutes one page. The entire cells share a P well. The NAND flash memory device further includes a pass transistor for applying a specific voltage to the cell blocks. The pass transistor includes a high voltage transistor for drain selection, a high voltage transistor for source selection, and a high voltage transistor for cell selection.
In the NAND flash memory device constructed above, in order to program data into a memory cell, erasure is performed, and a program operation is then performed on only a selected group of cells. In this case, the program operation of the NAND flash memory device is performed on a page basis, but the erase operation thereof is performed on a cell-block basis since the entire cells share the P well. An erase method of the conventional NAND flash memory device is described below in short.
After any one of the plurality of cell blocks is selected, a power supply voltage is applied to a gate terminal of each of a high voltage transistor for drain selection, a high voltage transistor for source selection, and a high voltage transistor for cell selection within a pass transistor connected to the selected cell block. A voltage of 4.5 V is applied to a drain select transistor and a source select transistor through the high voltage transistor for drain selection and the high voltage transistor for source selection, and a voltage of 0 V is applied to a memory cell through the high voltage transistor for cell selection.
Further, a voltage of 0 V is applied to a gate terminal of each of a high voltage transistor for drain selection, a high voltage transistor for source selection, and a high voltage transistor for cell selection within a pass transistor connected to an unselected cell block. An erase voltage is applied to P wells of the entire cell blocks. However, in P wells of an unselected cell, when the erase voltage rises, a word line voltage of an unselected cell block rises due to the coupling effect incurred by capacitance of the word lines and capacitance between the word lines and the P well. Accordingly, the unselected cell block is not erased.
FIG. 1 is a circuit diagram of a block switch circuit of a conventional flash memory device.
Referring to FIG. 1, a block selection circuit 10 outputs a block select signal (Bsel) in response to a plurality of decoded block addresses BA0 to BAi, and selects a memory block.
At the time of an erase operation, the flash memory device performs the erase operation by individually specifying a block address on which the erase operation will be performed. Due to this, a memory controller has to designate a block address for every block, and an erase time increases in proportion to the number of blocks designated.